1. Field of the Invention
The present invention relates to the field of flat panel display technology, in particular to an array substrate, a manufacturing method thereof, and a flat panel display device.
2. Description of Related Arts
People have increasing demand for display devices so that flat panel display can be widely popular, and the LCD (Liquid Crystal Display) and the OLED (Organic Light-Emitting Diode) industries are rapidly developing.
The array substrate is an important element of the display panel, which has an effective display region (referred to AA region, Active Region) and a non-effective display region surrounded the effective display region, the effective display region includes signal lines, scan lines and data lines. The non-effective region includes fan-out leads distributed as a fan shape. The signal lines connect correspondingly to the fan-out leads, and connect to the periphery chip through the fan-out leads. Since the length of each fan-out lead is not equal, if the width of each fan-out leads case is equal, the impedances of the fan-out leads at the central portion of the fan shape are lower than the impedances of the fan-out leads at the edge portion of the fan shape. Therefore, when sending a signal to the signal lines, the signal outputted by the chip cannot keep synchronization so as to cause the display unevenness.
Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a schematic drawing of the fan-out leads in the prior art. In FIG. 1, it only schematically illustrates three fan-out leads. The fan-out lead 11, fan-out lead 12, and fan-out lead 13 are distributed as a fan shape. The fan-out lead 12 is located at the center of the fan shape, and the fan-out leads 11 and 13 are located at the edges of the fan shape. The lengths of the fan-out lead 11 and the fan-out lead 13 are equal. The fan-out lead 12 utilizes a bending winding way to increase the effective length such that its length is consistent with the lengths of the fan-out lead 11 and the fan-out lead 13. FIG. 2 is a cross-sectional view of the fan-out leads 12 shown in FIG. 1 at the A-A′ direction.
The fan-out lead 12 is obtained by sequentially stacking a first metal layer 121, an insulation layer 122, a second metal layer 123 and a passivation layer 124 and by using the array process. Since the first metal layer 121 and the second metal layer 123 are insulated from each other, when a signal is input, the first metal layer 121 and the second metal layer 123 are equivalent to two resistors connected in parallel. The fan-out lead 11 and the fan-out lead 13 have the same internal structures with the fan-out lead 12.
Because each of the fan-out leads has the same structure, and their lengths are also the same, the fan-out lead 11, the fan-out leads 12 and the fan-out lead 13 have equal impedance. However, because the limitation of the conventional art and process, the winding portion of the fan-out lead 12 is relatively sparse such that the height of the fan-out lead 12 is increased, and the area occupied by the non-effective display region is increased. Therefore, it is not conducive for the narrow frame design of the display panel, and reduces the utilization rate of the array substrate.